Design of optimized Proposed 9T SRAM Cell
نویسندگان
چکیده
منابع مشابه
Design and Analysis of Power Efficient 9t Adiabatic Sram Cell
Leakage power is becoming the dominant power component in deep submicron technology and stability of the data storage of SRAM (Static Random Access Memory) cells is drawing more concerns with the reduced feature sizes. A novel 9T SRAM cell design considering these leakage issues for ultra low power applications is proposed in this paper. The elementary cell structure of proposed adiabatic SRAM ...
متن کاملMTJ-Based Nonvolatile 9T SRAM Cell
This paper presents a spin-transfer torquemagnetic tunnel junction (STT-MTJ) based non-volatile 9-transistor (9T) SRAM cell. The cell achieves low power dissipation due to its series connected MTJ elements and read buffer which offer stacking effect. The paper studies the impact of PVT (process, voltage, and temperature) variations on the design metric of the SRAM cell such as write delay and c...
متن کاملA Comparative Study of 6T, 8T and 9T SRAM Cell
From the last few decades, the scaling down of CMOS devices have been taking place to achieve better performance in terms of speed, power dissipation, size and reliability. The major area of concern in today‟s CMOS technology is Data retention and leakage current reduction. SRAM (Static Random Access Memory) is memory used to store data. Conventional Static Random Access Memory (SRAM) cells suf...
متن کاملA Column-decoupled 9t Cell for Low Power Differential and Domino-based Sram Design
Embedded memories are widely used in low power system on chip. Low power performance can optimized with process, circuit, architecture and system level codevelopment. Static random access memories consist of almost 90% of Very Large Scale Integration (VLSI). In this project, Low power design considerations are described in advanced technology nodes to address memory leakage and active power dis...
متن کاملA Sub-threshold 9T SRAM Cell with High Write and Read ability with Bit Interleaving Capability
This paper proposes a new sub-threshold low power 9T static random-access memory (SRAM) cell compatible with bit interleaving structure in which the effective sizing adjustment of access transistors in write mode is provided by isolating writing and reading paths. In the proposed cell, we consider a weak inverter to make better write mode operation. Moreover applying boosted word line feature ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: IJARCCE
سال: 2017
ISSN: 2278-1021
DOI: 10.17148/ijarcce.2017.6447